This invention relates to an MOS transistor circuit for precharging a plurality of bus lines over which data logic signals are transferred.
In a logical operation system provided with an ALU (arithmetic and logic unit) a plurality of parallel bus lines are utilized to transfer logic signals whose bits correspond to the number of the bus lines. In a system where 8 parallel bus lines are used to transfer 8-bit logic signals, for example, a selected number of bus lines out of the 8 are discharged after an initial precharging of all of the lines to thereby transfer the 8-bit binary signal to an ALU. The 8 parallel bus lines are then precharged again in response a clock signal, and another set of selected bus lines is discharged to transfer another 8-bit signal through them. The ALU may then add the two 8-bit signals and store the result in a register, for example.
To precharge a plurality of parallel bus lines as described above, a conventional MOS transistor circuit comprised of 8 PMOS transistors T.sub.1 -T.sub.8 for 8 parallel bus lines 1 through 8 has been used, as shown in FIG. 1 for example. These MOS transistors have first electrodes connected to a common voltage source V, and second electrodes individually connected to the respective bus lines. Each of their gate electrodes is connected to a common clock signal line .phi.. Each parallel bus line has a parasitic capacitance represented by capacitors C.sub.1 through C.sub.8 connected to the ground G.
In this conventional circuit, when the clock signal line becomes "L" or low at the precharge period, the PMOS transistors T.sub.1 -T.sub.8 are turned on and all of the bus lines 1-8 are pulled up to the "H" or high state to charge the capacitors C.sub.1 -C.sub.8.
The clock signal line .phi. then becomes "H" to turn off all of the PMOS transistors T.sub.1 -T.sub.8 and hold the capacitors C.sub.1 -C.sub.8 in their precharging state.
Assuming that the bus lines 3, 6 and 7 are now pulled down to "L" and the other bus lines 1, 2, 4, 5 and 8 are kept in the "H" state, an 8-bit data signal 11011001 will be transferred through the parallel bus lines to the ALU. The "L" state corresponds to a logic "0", and the "H" state corresponds to a logic "1". All of the bus lines are then precharged again through the transistors T.sub.1 -T.sub.8 when the clock signal .phi. goes low, in preparation for the next transfer cycle.
Since capacitors C.sub.1, C.sub.2, C.sub.4, C.sub.5 and C.sub.8 were previously charged up to the source voltage level V and were not discharged during the signal transfer, their precharging or recharging is performed in an extremely short time period. Capacitors C.sub.3, C.sub.6 and C.sub.7 were discharged, on the other hand, and it thus takes considerably more time to precharge them back up to the source voltage V through transistors T.sub.3, T.sub.6 and T.sub.7. Moreover, since the bus lines 3, 6 and 7 which have been pulled down to "L" and the bus lines 1, 2, 4, 5 and 8 which have not been pulled down must be equally precharged, the PMOS transistors T.sub.1 -T.sub.8 must each have enough driving capacity to charge a bus line up to the source voltage level during the precharge period. Finally, since each of the bus lines is exclusively charged through its individual PMOS transistor, variations in the voltage level of the bus lines result when the precharge time is set too short.